Objectives: Familiarize the students with the architecture of a CMOS imager and or a computational vision microsystem.

Four different chip designs will be used to become familiar with the architecture of CMOS imager and vision microsystems.

vid1amit: A random access 32 x 32 phototransistor imager  array. Fabricated in the MOSIS AMI 1.2 micron (now AMI 1.5) n-well process run M86O. Chip designed by Z. Kalayjian and discussed in the mismatch characterization paper reference 6. Ledit file.

vid1amid: A photodiode version of the above chip.Ledit file.

A gallery of photomicrographs for this chip can be found here

vc2: A scanned 31 x 31 phototransistor imager array  and an embedded centroid computational circuit. Fabricated in the MOSIS Orbit 2.0 micron n-well process.Chip designed by K. Strohbehn and discussed in the photodiode and phototransistor characterization paper reference 7 (unpublished report) and in the published conference paper reference 8. Ledit file.

dcamn: A dual analog/digital output 32 x 32 phototransistor imager array with  on chip A/D converter to produced a digital output as well as a current output. Fabricated in the MOSIS AMI 1.2 micron  (now AMI 1.5) n-well process. Designed by Z. Kalayjian in support by Nissan corporation (Shinji Nakamura). The design of the chip is described in reference 9 (unpublished report). Ledit file.

dcamn2: A photodiode version of the above chip. Ledit file.

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II. Lab Work:

Download ONE design of your choice and open it in LEDIT.. Navigate around to identify the Pads, the scanners, the photosensitive array, the video amplifier.

Construct a circuit diagram for the circuit in the basic cell  (the one that is replicated N x N times  to form the photosensitive array). Include transistor types and size (in microns).

How big are the bonding pads? (in microns).

How big are the photosensitive elements (in microns).