Analog IC Design: CMOS Imagers and Vision Microsystems

Laboratory Assignment #1

Objectives: To familiarize students with Ledit and CMOS layout.

The pop2um chip was designed by Philippe O. Pouliquen to help with prototyping test circuits using transistors in subthreshold. The chip contains NMOS and PMOS transistors that have large W/L ratio and thus can operate at large current levels and still be in subthreshold.. The chips that we have in the lab were fabricated in a 2 um ORBIT/Supertex,  n-well process  through the MOSIS foundry. The Ledit file for the chip is here and the CIF file here.

When the chips arrive from MOSIS, a bonding map is included in the package. This map provides the link between the internal pad positions on the die and the external pins of the package. The bonding map for this particular chip can be downloaded here.

We will use the MOSIS AMI 1.5 micron technology for all the designs that we do. You can find technology definition files and TSPICE models here. ALWAYS start with these by COPYING them into a new directory.

I. Prelab Work:

None

II. Lab Work:

1. Tutorial introduction to Tanner tools:

Follow the Tanner tools tutorials to learn how to use SEDIT, LEDIT,  LVS and TSPICE. Use SEDIT to capture the schematic for the 7 CMOS inverter ring oscillator. Simulate the ring oscillator using TSPICE. Using LEDIT do the layout for the ring oscillator in the MOSIS 1.2 micron AMI process (including the load capacitor using poly1/poly2), and extract the circuit. Simulate the circuit using TSPICE. Compare the results of extracted simulation with that from the SEDIT circuit. Run LVS to compare the layout with the one captured using SEDIT.

2. Working with the pop2um chip

Open the pop2um in Ledit. 

Navigate around the chip and produce a circuit diagram for the whole chip. Note that the circuits/devices in the middle of the chip all connect to the pads in the pad ring. Using the schematic capture program, draw the diagram for the circuits on the chip. Include the dimensions of the transistors on your layout.

Extract the layout of the chip and use LVS to compare your schematic with the one that Ledit extracted.

Knowing that this chip was fabricated at MOSIS on the N86M run, download from the MOSIS web site the parametric test results for this process. Print them and keep them for your information.

3. Design a small circuit of your choice

Starting with a CLEAN technology file. Design a small circuit (a few transistors). Simulate, do layout, extract, LVS and simulate your layout. 

III. Postlab Work:

Compare the the schematic capture file and the output file produced by LVS (showing that your circuit is correct)  by email to the instructor (PDF or Word file).

Send the instructor an email  that includes your ledit file of your design. This is what we will fabricate. Do not include the design in a frame.