CAD TOOLS:

We use the Tanner tools as well as Cadence and Magic for chip design.

Tanner Tools

Fabrication:

Integrated circuits designed in our courses are fabricated through the  MOSIS (MOS Implementation System) silicon foundry with support from the NSF educational program and or grants from DARPA, ONR and ARL.

Parametric results and SPICE model parameters for MOSIS processes:

MOSIS provides parametric data, such as layer resistivity, capacitance between layers and nominal MOS transistor model parameters for all the fabrication runs in all technologies. The files for the recent MOSIS runs as well as not so recent runs are here.